1. Field of the Invention
The present invention relates to a semiconductor device and dummy pattern arrangement method.
2. Description of Related Art
A semiconductor device has recently been developed to be more multi-layered. When a plurality of wiring layers are laminated in several layers, the wiring layer in an upper layer is influenced by convex/concave in the surface of the wiring layer in a lower layer. If this influence is large, there is a possibility that disconnection is occurred in wirings in the wiring layer formed in the upper layer in some cases. Even in the same wiring layer, the wirings may be disconnected due to partial convex/concave. In order to solve the problem, there is proposed a technique for arranging dummy patterns for each of the plurality of wiring layers in a region where the wiring patterns are not formed (see Japanese Unexamined Patent Application Publication No. 2002-368088, Japanese Unexamined Patent Application Publication No. 2000-277615, Japanese Unexamined Patent Application Publication No. 2003-140319, and Japanese Unexamined Patent Application Publication No. 2004-253655).
For example, Japanese Unexamined Patent Application Publication No. 2002-368088 discloses a technique for simplifying capacity calculation of parasitic capacity added to the wiring patterns by making distance between the dummy patterns and the wiring patterns constant. Further, Japanese Unexamined Patent Application Publication No. 2000-277615 discloses a technique arranging the dummy patterns having different densities in a region where the wiring patterns of the wiring region are not arranged.
By the way, manufacturing process has recently become more and more miniaturized and the distance between wirings has become shorter due to the miniaturization. Therefore, the distance between the dummy pattern and the wiring pattern has been decreased. When the distance between the dummy pattern and the wiring pattern is decreased, a resist may lie during a manufacturing process and the wiring pattern and the dummy pattern may be connected (shorted out) by dust (defect).
Normally, potential of each of the dummy patterns is set to a floating state (a state where no connection is made). Therefore, even when the wiring pattern and the dummy pattern are connected by dust as described above, a behavior of the semiconductor device is not immediately damaged. However, when the wiring pattern and the dummy pattern are connected by dust, unintentional wiring capacity and resistance are added to the wiring pattern. When the unintentional wiring capacity and resistance are added to the wiring pattern, unintentional propagation delay of the signal may be caused. The unintentional propagation delay of the signal not always cause malfunction of the semiconductor device. However, malfunction of the semiconductor device may be caused in some cases. Note that the function of the semiconductor device may be immediately damaged when the wiring pattern and the dummy pattern are connected by dust in a state where the dummy pattern is connected to power supply potential (VDD, GND).
Japanese Unexamined Patent Application Publication No. 2002-368088 discloses a layout where dummy patterns are arranged continuously in the direction perpendicular to the wiring patterns extending in one direction. Although the dummy patterns are arranged separately from the wiring patterns, if one end of the dummy pattern and the wiring pattern are shorted out by dust, the capacity of the dummy pattern is added to the wiring pattern.
On the other hand, in Japanese Unexamined Patent Application Publication No. 2000-277615, there is disclosed a technique arranging dummy patterns having different densities. In this case, the dummy patterns having low metal densities are arranged close to the wiring patterns and therefore it is suppressed that the wiring capacity is added to the wiring pattern by dust. However, when the technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-277615 is applied, data amount required to execute dummy pattern arrangement process is increased.
In Japanese Unexamined Patent Application Publication No. 2000-277615, arrangement region of the pattern is divided into a plurality of blocks, and pattern having high metal density and pattern having low metal density are arranged in each block. The arrangement position of each pattern is identified using apex information (apex coordinate or the like) of each pattern included in the wiring data (layout data). Therefore, the technique for dividing the wiring region into the plurality of blocks as in Japanese Unexamined Patent Application Publication No. 2000-277615 requires setting the apex information of the pattern for each block after being divided, which increases data amount required for dummy pattern arrangement.
For example, when the wiring region of the semiconductor chip of 10 mm*10 mm is divided into blocks of 0.2 μm*0.2 μm, the number of blocks that is set reaches 2.5*109. When the dummy patterns are arranged in all the blocks, the apex information of the dummy patterns corresponding to the number of blocks that are set is needed and data amount required for dummy pattern arrangement is increased. The increase in the data amount required for dummy pattern arrangement causes longer time for wiring process and memory shortage of the wiring device.
As stated above, an arrangement method for preventing the decrease of the reliability of the semiconductor device due to the attachment of dust between the patterns without increasing data amount for dummy pattern arrangement is required. A semiconductor device having a dummy pattern arrangement layout for preventing the decrease of the reliability of the semiconductor device due to the dust attachment between the patterns is also required.